1. Field of the Invention
The present invention relates to image reading devices that optically read an image of an original. The present invention relates more particularly to an image reading device that can control a variation in an image level.
2. Description of the Related Art
In association with higher image quality and higher speed required of image forming apparatuses such as digital copiers, higher pixel density and higher speed upon image reading are also required of image reading devices provided in the image forming apparatuses. Digital copiers, facsimiles, and digital multifunction products are the examples of such image forming apparatuses.
FIG. 36 is a block diagram of a signal processing system in a conventional digital copier. Signal processing from reading of an image by a photoelectric conversion device to converting of the image to a digital image signal is implemented in the following manner as shown in FIG. 36.
More particularly, a source oscillation clock generated and output from an oscillator (OSC) 1 is converted to a frequency-modulated clock by a spectrum spread clock generator (SSCG) circuit 2. The frequency-modulated clock is input to a phase locked loop (PLL) circuit 3a in a timing-generation integrated circuit (IC) (TG: timing generator) 3. The PLL circuit 3a generates clocks CCD_CLK and AFE_CLK by multiplying the received clock and outputs the generated clocks CCD_CLK and AFE_CLK to a charge-coupled device (CCD) 4 and a signal processing IC (AFE: analog front-end) 5 respectively as drive clocks. The CCD 4 receives light reflected from an original, converts the light to an electrical signal, and outputs the electrical signal to the AFE 5 through a buffer (EF: emitter follower) 6 and an alternating-current (AC)-coupled capacitor 7. The AFE 5 includes a clamp circuit (CLMP) 5a, a sample hold circuit (SH) 5b, a programmable gain circuit (PGA) 5c, and an analog-to-digital (A/D) converter (ADC) 5d. A zero level (black level) of a received image signal (Vsig) is corrected to an internal reference voltage (Vref) by the CLMP 5a and input to the SH 5b. The received image signal is sample-held by the SH 5b by using the internal reference voltage (Vref), the resulting signal is amplified by the PGA 5c, and the resulting signal is A/D-converted by the ADC 5d. A 10-bit digital image signal (DOUT [9:0]) obtained in this process is output to the next stage.
Speeding up of image reading devices has disadvantageously led to generation of undesired radiation (EMI). The SSCG 2 is typically employed these days to prevent generation of undesired radiation (EMI). The SSCG 2 cyclically modulates the frequency of a received clock signal. More specifically, as shown in FIG. 37, the SSCG 2 is operative to reduce a peak level of radiation noise per unit time from S1 to S2 by applying a frequency spread to the received clock signal.
In the conventional technology, however, because the frequency-modulated clock is used in the CCD 4 and the AFE 5, there is a problem that the image signal varies according to a modulation period of the SSCG 2 (see FIG. 38). If the image signal varies, an offset level of an output signal varies in the CCD 4 and a sample-holding timing varies in the AFE 5. The variation caused by the SSCG 2 is generally asynchronous to a main scanning line, and therefore phases of variations are gradually shifted in order from a first line, a second line, . . . , as shown in FIG. 39. As a result, oblique stripes appear in a read image. FIG. 39 is a diagram in which level variations in image signals of the lines are arranged in a sub-scanning direction. In an actual output image, portions of a low image level (dips) become high (dark) in image density, while portions of a high image level (peaks) become low (light) in the image density. Consequently, stripes appear on a straight line connecting the portions of the low image level of the respective lines and on a straight line connecting the portions of the high image level of the respective lines.
Japanese Patent Application Laid-open No. 2008-118366 discloses a technology to prevent generation of the stripes. This technology removes a variation component from an image signal to prevent generation of horizontal stripes. The disclosed image reading device has functions of converting an incident light into an analog image signal by a photoelectric conversion device, digitizing the analog image signal by a analog-to-digital converter, and outputting the digitized image signal. The image reading device includes a unit that drives the photoelectric conversion device using a frequency-modulated clock, and is characterized in that a signal is superimposed on the image signal. Specifically, the signal has an opposite phase and an equal amount of variation to a variation of the analog image signal according to a change in frequency of the clock.
Japanese Patent Application Laid-open No. 2005-151296 also discloses a technology to prevent generation of the stripes.
However, a variation in an image signal level due to SSCG (hereinafter, “variation due to SSCG”) occurs as a composite result of variations generated in various elements such as the SSCG, the CCD, the TG (VCO gain in the PLL circuit), the AFE, and drive circuits and circuit patterns of these components. Therefore, the variation due to SSCG can vary greatly from one signal processing system to another; i.e., there is a large individual difference (variation) in the variation level itself. Consequently, in the technology disclosed in Japanese Patent Application Laid-open No. 2008-118366, it is not possible to deal with the variation when the individual difference becomes significant (e.g., when the signal processing systems are produced in large numbers or the like) although the variation can be principally corrected. For example, if correction is performed on a component without the variation due to SSCG, and the variation is thereby worsened rather than being corrected.